1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a structure and a manufacturing method of a metal-oxide-silicon field-effect transistor having a trench gate (trench MOSFET) formed on the same substrate with MOS transistors.
2. Description of the Related Art
MOS transistors are electronic devices playing a central role in electronics. Reducing the size of the MOS transistors and improving the driving performance thereof have been important challenges regardless in a low withstanding voltage region or in a high withstanding voltage region.
Since a transistor having a large channel width in a small area can be formed in a vertical trench MOSFET, in which vertical movement of carriers are generated, the vertical trench MOSFET is generally used in an application in which high driving performance is needed. Vertical trench MOSFETs have been widely used as discrete driver elements until now, but in recent years there has been proposed a manufacturing process of integration of the trench MOSFET having high driving performance with CMOS transistors forming a control circuit.
In many cases, the trench MOSFET has a vertical double diffused MOS (DMOS) structure, in which a region generally called a P-body has a portion which is held in contact with the gate oxide film and which works as a channel forming region. The concentration of the P-body region is set higher than that of a region of the adjacent drain having a relatively low impurity concentration. In this case, when a high voltage is applied to the drain, more extension of the depletion layer is generated in the drain than in the P-body, permitting suppression of lowering in breakdown voltage caused by a punch-through, in which the depletion layer extending from the drain reaches the source region. Accordingly the breakdown voltage can be ensured even when the channel length of the transistor is made short. Consequently there is a feature that an element having high driving performance can be easily obtained.
However, the resistance increases in inverse proportion to the impurity concentration in the region of the drain having a relatively low impurity concentration, and hence in consideration of the junction breakdown voltage, the impurity concentration thereof is desired to be set high to some extent. When the concentration of the P-body at this time is not changed, the depletion layer greatly expands to the P-body region side, causing reduction in punch-through breakdown voltage. On the other hand, when the impurity concentration of the P-body is increased in response to the drain impurity concentration, the increase may cause reduction in junction breakdown voltage and rise of a threshold voltage.
Conventionally, in order to maintain the breakdown voltage and suppress a drain parasitic resistance as much as possible, the following methods have been employed. That is, the impurity concentration of the P-body region and the concentration of the drain are adjusted, or alternatively, as described in Japanese Published Patent Application No. 2000-164869, a mask alignment/exposure step and an impurity implantation step are added to an epitaxial (Epi) step. In this manner, reduction in punch-through breakdown voltage due to the expansion of the depletion layer in the P-body region is suppressed.
In the technology described in Japanese Published Patent Application No. 2000-164869, as illustrated in FIG. 5, a trench MOSFET 30 is formed in a structure including a P type epitaxial layer 34 corresponding to an upper layer of an N+ type substrate 32. (Here, notation of N+ represents a heavily doped N type region.) An N type drain region 33 is formed by implantation into the P type epitaxial layer through a bottom portion of a trench 35, and then the N type drain region 33 is subjected to a diffusion step. In this manner, the N type drain region 33 is formed to extend between the N+ type substrate 32 and the bottom portion of the trench. A junction portion 33a between the N type drain region and the P type epitaxial layer 34 extends between the N+ type substrate and a side wall of the trench.
As described above, in this technology, the N type drain region 33 is formed by implantation into the P type epitaxial layer at the bottom portion of the trench 35, and hence the P-body region is formed shallow in the vicinity of the side wall of the trench, and is formed deep in a region distanced from the trench. In this manner, while controlling the channel length to be short to some extent, the punch-through breakdown voltage, at which the depletion layer reaches to the source side from the drain, is improved. This is because the depletion layer extending from the drain has a maximum extension in a region at some distance from the channel. In order to improve the breakdown voltage, it is effective to control the depletion layer in the region at some distance from the channel region just below the gate.
However, in the technology described in Japanese Published Patent Application No. 2000-164869, in order to change the depth of the P-body in the vicinity of the trench side wall, which determines the channel length, and the depth of the P-body in a region at some distance from the trench, a mask alignment/exposure step is added and then ion implantation is performed, with the result that the number of manufacturing steps increases. Further, because ion implantation is performed through the trench, there are many parameters that may cause increase in fluctuations, such as a trench width, a trench depth, an insulating film thickness of the trench side wall, and an angle of the ion implantation, and hence it is extremely difficult to perform precise control. Fluctuations in the channel length of the transistor, fluctuations in a drain resistance layer, and further fluctuations in many transistor characteristics are thus unavoidable.